Waveform Analysis Language

A programming language for complex waveform analysis and EDA tool development

Install WAL with Pip

Browse the WAL documentation



(in-groups '("top.in_" "top.out_")
  (print CG ":")
  (whenever (&& clk (! reset) #ready #valid)
(print INDEX ":" #data)))

Natural Expression of Hardware Problems

WAL knows what matters in the hardware domain. With WAL it is possible to access signals, step through the waveform or explore the design hierarchy without hundreds of lines of boilerplate.

(clk reset comp1.ack comp1.req)
>-> (find (&& comp1.ack comp1.req))
(15 26 102)

Interactive Development

WAL has a REPL and can be used for interactive debugging, design understanding, and live WAL programming.

bug_locations = wal.eval("(find condition)")
for loc in bug_locations:
    bug = Bug("Unacknowledged", bug_location)
Works for you

WAL is a Python package and can be implemented in virtually every workflow. You can use it embedded in Python like SQL or write standalone WAL scripts.

WAL at Upcoming Events

Workshop Open-Source Design Automation (OSDA 2023)
Monday, 17 April 2023. Antwerp, Belgium
Co-located to the DATE conference.


WAL @ DVCON Europe'22

In December, together with MINRES Technologies we presented a joint paper at the DVCON Europe in Munich. In this paper, we extended our RISC-V processor analysis with WAL to MINRES' The Good Core line of RISC-V processors.

WAL 0.6.3 beta released

The beta version for WAL 0.6.3 is now available on GitHub. This version adds support for the FST waveform format, the fast PyPy interpreter, and brings a lot of additional optimizations.

WAL @ DAC'22

We will present WAL on Wednesday, July 13th6:00pm at the DAC Late Breaking Results poster session.
In this paper we present how generic performance analysis of RISC-V cores is possible using WAL. Our RISC-V analysis WAL package is easily applicable to new RISC-V cores.
You can find the paper here and the WAL code used in the experiments on GitHub.

WAL Screencast

In this screencast we show how WAL can be used to analyze the average number of cycles the SERV and VexRiscv cores need to execute one instruction.
To compute this value we analyze the number of instructions that are executed by each core and divide it by the number of clock cycles of the complete waveform. In the SERV core whenever the execution of a new instruction starts the signal wb_ibus_ack on the instruction bus is set to high. Similarily, in the VexRiscv core we know an instruction was executed when the isFiring signal of the last pipeline stage is set to high.